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82912hkpc 018-11-0017 no. a2116-1/27 STK672-640C-E overview the STK672-640C-E is a hybrid ic for use as a unipolar, 2-phase stepping motor driver with pwm current control. applications ? office photocopiers, printers, etc. features ? built-in opened motor pin detection function (output current off). ? built-in overcurrent detection function (output current off). ? built-in overheat detection function (output current off). ? if opened motor pin, over-current, or overheat detection function is activated, the fault1 signal (active low) is output. the fault2 signal is used to output the result of activation of protection circuit detection at 3 levels. ? built-in power on reset function. ? the motor speed is controlled by the frequency of an external clock signal. ? 2 phase or 1-2 phase excitation switching function. ? using either or both edges of the clock signal switching function. ? phase is maintained even when the excitation mode is switched. ? rotational direction switching function. ? supports schmitt input for 2.5v high level input. ? incorporating a current detection resistor (0.089 : resistor tolerance 2%), motor current can be set using two external resistors. ? the enable pin can be used to cut output current while maintaining the excitation mode. ? with a wide current setting range, power consumption can be reduced during standby. ? no motor sound is generated during hold mode due to external excitation current control. ordering number : ena2116 thick-film hybrid ic 2-phase stepping motor driver specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. the products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appli ances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliab ility and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. if there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
STK672-640C-E no. a2116-2/27 specifications absolute maximum ratings at tc = 25 c parameter symbol conditions ratings unit maximum supply voltage 1 v cc max no signal 50 v maximum supply voltage 2 v dd max no signal -0.3 to +6.0 v input voltage v in max logic input pins -0.3 to +6.0 v output current 1 i op max 10 a, 1 pulse (resistance load) 20 a output current 2 i oh max1 v dd =5v, clock 200hz 4 a output current 3 i oh max2 v dd =5v, clock 200hz v cc 29v 4.5 a output current 4 i of max pin16 output current 10 ma allowable power dissipation 1 pdmf max with an arbitrarily large heat sink. per mosfet 8.3 w allowable power dissipation 2 pdpk max no heat sink 3.1 w operating substrate temperature tc -20 to +105 c junction temperature tj max 150 c storage temperature tstg -40 to +125 c allowable operating ranges at ta=25 c parameter symbol conditions ratings unit operating supply voltage 1 v cc with signals applied 10 to 46 v operating supply voltage 2 v dd with signals applied 5 5% v input high voltage v ih pins 10, 12, 13, 14, 15, 17 v dd =5 5% 2.5 to v dd v input low voltage v il pins 10, 12, 13, 14, 15, 17 v dd =5 5% 0 to 0.8 v output current 1 i oh 1 tc=105 c, clock 200hz, continuous operation, duty=100% 3.0 a output current 2 i oh 2 tc=80 c, clock 200hz, continuous operation, duty=100%, see the motor current (i oh ) derating curve 3.3 a output current 3 i oh 3 tc=105 c, clock 200hz, v cc 29v continuous operation, duty=100%, see the motor current (i oh ) derating curve 3.5 a output current 4 i oh 4 tc=80 c, clock 200hz, v cc 29v continuous operation, duty=100%, see the motor current (i oh ) derating curve 3.8 a clock frequency f cl minimum pulse width: at least 10 s 0 to 50 khz recommended vref range vref tc=105 c 0.14 to 1.38 v electrical characteristics at tc=25 c, v cc =24v, v dd =5.0v parameter symbol conditions min typ max unit v dd supply current i cco pin 9 current clock=gnd 5 8 ma output average current* ioave r/l=1 /0.62mh in each pha se 0.519 0.625 0.731 a fet diode forward voltage vdf if=1a (r l =23 ) 0.83 1.5 v output saturation voltage vsat r l =23 0.20 0.33 v input high voltage v ih pins 10, 12, 13, 14, 15, 17 2.5 v input low voltage v il pins 10, 12, 13, 14, 15, 17 0.8 v fault1 low output voltage v olf pin 16 (i o =5ma) 0.25 0.5 v 5v level fault leakage current i ilf pin 16=5v 10 a fault2 opened motor pin detection output voltage v of 1 0.00 0.01 0.20 fault2 overcurrent detection output voltage v of 2 2.4 2.5 2.6 fault2 overheat detection output voltage v of 3 pin 8 (when all protection functions have been activated) 3.1 3.3 3.5 v 5v level input current i ilh pins 10, 12, 13, 14, 15, 17=5v 50 75 a gnd level input current i ill pins 10, 12, 13, 14, 15, 17=gnd 10 a vref input bias current i ib pin 19=1.0v 1 a continued to the next page.
STK672-640C-E no. a2116-3/27 continued from the previous page. parameter symbol conditions min typ max unit pwm frequency fc 29 45 61 khz overheat detection temperature tsd design guarantee 144 c drain-to-source leakage current i dss v ds =100v, pins 2, 6, 9, and 18=gnd 1 a * maximum value of operating supply voltage 1 (v cc ) can not supply to STK672-640C-E, depending on motor current value. refer to ?8. precauti ons, etc? of usage notes. *ioave values are for when the lead frame of the product is soldered to the mounting substrate. notes: a fixed-voltage power supply must be used.
STK672-640C-E no. a2116-4/27 package dimensions unit:mm (typ) derating curve of motor current, i oh, vs. STK672-640C-E operating substrate temperature, tc notes ? the current range given above represents conditions wh en output voltage is not in the avalanche state. ? if the output voltage is in the avalanche state, see the allowable avalanche energy for stk672-6** series hybrid ics given in a separate document. ? the operating substrate temperature, tc, given abov e is measured while the motor is operating. ? because tc varies depending on the am bient temperature, ta, the value of i oh , and the continuous or intermittent operation of i oh , always verify this value using an actual set. ? the tc temperature should be checked in the cent er of the metal surface of the product package. 29.2 25.6 (20.47) (5.0) (12.9) (5.6) 1.0 4.2 8.2 (20.4) 0.52 0.4 4.5 119 7.2 14.5 11.0 (5.0) (r1.7) (3.5) 2.0 14.5 14.4 18 1.0=18.0 5.0 0.5 0 080 20 40 60 100 70 10 30 50 90 110 3.0 4.5 4.0 3.5 2.5 1.0 1.5 2.0 i oh -tc operating substrate temperature, tc - c motor current, i oh - a 200hz 2phaseex/v cc 29v 200hz 2phase/v cc 46v hold/v cc 29v hold/v cc 46v
STK672-640C-E no. a2116-5/27 block diagram sample application circuit STK672-640C-E + 9 12 10 17 13 15 14 16 19 18 6 2 5 4 1 3 v dd (5v) clock mode1 mode2 enable resetb fault1 a ab b bb vref r01 r03 r02 c02 0.1 f 2 phase stepping motor driver 8 fault2 cwb p.gnd v dd v ss fao fab fbo fbb ai bi vref vref/4.9 amplifier r1 r2 v ss fault2 8 vrefop 7 a 4 ab 5 b 3 bb 1 excitation mode selection phase excitation signal generator phase advance counter fault1 fault2 signal overheating detection latch circuit latch circuit current control chopper circuit latch circuit power-on reset mode1 10 n.c 11 mode2 17 enable 15 fault1 16 n.c 18 v dd =5v 9 vref 19 clock 12 cwb 13 resetb 14 f1 f2 f3 f4 p. g 1 6 p. g 2 2 output open detection overcurrent detection
STK672-640C-E no. a2116-6/27 precautions [gnd wiring] ? to reduce noise on the 5v system, be sure to place the gnd of c01 in the circuit given above as close as possible to pin 2 and pin 6 of the hybrid ic. also, to achieve accurate current settings, be sure to connect vref gnd to the point where p.g1 and p.g2 share a connection. [input pins] ? if v dd is being applied, use care that each input pin does not apply a negative voltage less than -0.3v to pg and do not apply a voltage greater than or equal to v dd voltage. ? do not wire by connecting the circuit pattern on the p.c.b side to n.c pins. shown in the internal block diagram. ? ? apply 2.5v high level input to pins 10, 12, 13, 14, 15, and 17. ? since the input pins do not have built-in pull-up resistors, wh en the open-collector type pins 10, 12, 13, 14, 15, and 17 are used as inputs, a 1 to 20k pull-up resistor (to v dd ) must be used. at this time, use a device for the open collector driver that has output current specifications that pull the voltage down to less than 0.8v at low level (less than 0.8v at low level when i ol =5ma). [current setting vref] if the motor current is temporarily reduced, the circuit given below (STK672-640C-E : i oh >0.3a) is recommended. ? motor current peak value i oh setting i oh =(vref 4.9) rs the value of 4.9 in equation above represents the vref voltage as divided by a circuit inside the control ic. vref=(r02 (r01+r02)) 5v(or 3.3v) rs is an internal current detection resistor value of the hybrid ic. rs=0.089 when using the STK672-640C-E 5v r01 r02 r3 5v r01 r02 r3 vref vref i oh 0
STK672-640C-E no. a2116-7/27 input pin functions pin name pin no. function input conditions when operating clock 12 reference clock for motor phase current switching operates on the rising edge of the signal (mode2=h) mode1 10 low: 2-phase excitation high: 1-2 phase excitation mode2 17 excitation mode selection high: rising edge low: rising and falling edge cwb 13 motor direction switching low: cw (forward) high: ccw (reverse) resetb 14 system reset initial state of a and bb phase excitation in the timing charts is set by switching from low to high. a reset is applied by a low level enable 15 the a, ab, b, and bb outputs are turned off, and after operation is restored by returning the enable pin to the high level, operation continues with the same excitation timing as before the low-level input. the a, ab, b, and bb outputs are turned off by a low- level input. output pin functions pin name pin no. function input conditions when operating fault1 16 monitor pin used when opened motor pin, over-current detection, or overheat detection function is activated. low level is output when detected. fault2 8 the result of activation of protection circuit detection is output. 3 levels output voltage vrefop 7 monitor pin of reference voltage used when opened motor pin detection. normal dc voltage output (typ98mv) note: see the timing chart for the concrete details on circuit operation.
STK672-640C-E no. a2116-8/27 timing charts 2-phase excitation 1-2 phase excitation power on reset (or resetb) v dd mode1 mode2 cwb clock enable fao fab fbo fbb power on reset (or resetb) v dd mode1 mode2 cwb clock enable fao fab fbo fbb
STK672-640C-E no. a2116-9/27 1-2 phase excitation (cwb) 2 phase excitation switch to 1-2 phase excitation power on reset (or resetb) v dd mode1 mode2 cwb clock enable fao fab fbo fbb power on reset (or resetb) v dd mode1 mode2 cwb clock enable fao fab fbo fbb
STK672-640C-E no. a2116-10/27 1-2 phase excitation (enable) 1-2 phase excitation (hold operation results during fixed clock) power on reset (or resetb) v dd mode1 mode2 cwb clock enable fao fab fbo fbb hold operation power on reset (or resetb) v dd mode1 mode2 cwb clock enable fao fab fbo fbb
STK672-640C-E no. a2116-11/27 2 phase excitation (mode 2) 1-2 phase excitation (mode 2) power on reset (or resetb) v dd mode1 mode2 cwb clock enable fao fab fbo fbb power on reset (or resetb) v dd mode1 mode2 cwb clock enable fao fab fbo fbb
STK672-640C-E no. a2116-12/27 usage notes 1. STK672-640C-E input signal functions and timing [enable, clock and power on reset, resetb (in put signal timing when power is first applied)] the control ic of the driver is equipped with a power on reset function capable of initializing internal ic operations when power is supplied. a 4v typ settin g is used for power on reset. because the specification for the mosfet gate voltage is 5v 5%, conduction of current to output at the time of power on reset adds electromotive stress to the mosfet due to lack of gate voltage. to prevent electromotive stress, be sure to set enable=low while v dd , which is outside the operating supply voltage, is less than 4.75v. in addition, if the resetb terminal is used to in itialize output timing, be sure to allow at least 10 s until clock input. enable, clock, and res etb signals input timing [clock (phase switching clock)] ? input frequency: dc to 50khz ? minimum pulse width: 10 s ? mode2=1(high) signals are read on the rising edge. ? mode2=0(low) signals are read on the rising and falling edges. [cwb (motor direction setting)] the direction of rotation is switched by setting cwb to 1 (high) or 0 (low). see the timing charts for details on the operation of the outputs. note: the state of the cwb input must not be changed during the 6.25 s period before and after the rising edge of the clock input. [enable (forcible on/off control of the a, ab, b, and bb outputs, and hybrid ic internal operation)] enable=1: normal operation enable=0: outputs a, ab, b, an d bb forced to the off state. if, during the state where clock signal input is provid ed, the enable pin is set to 0 and then is later restored to the 1 state, the ic will resume operatio n with the excitation timing continued from before the point enable was set to 0. if sudden stop is applied to the clock signal used for motor rotation, the motor axis may advance beyond the theoretical position due to inertia. to stop at the theore tical position, the slow down setting for gradually slowing the clock cycle is required. 4v typ 3.8v typ at least 10
STK672-640C-E no. a2116-13/27 [mode1 and mode2 (excitation mode selection)] mode1=0: 2-phase excitation mode2=1: rising edge of clock mode1=1: 1-2 phase excitation mode2=0: rising and falling edges of clock see the timing charts for details on output operation in these modes. note: the state of the mode input must not be changed during the 5 s period before and after the rising edge of the clock input. the clock input must not be changed during the period from when the signal changes from high to low or low to high in mode1 or mode2, till when the signal changes from high to low or low to high in cwb. [configuration of each input pin] cwb, enable, and resetb input pins> (configuration of the buffer is open drain.) all input pins of this driver support sc hmitt input. typ specifications at tc = 25 c are given below. hysteresis voltage is 0.3v (viha-vila). input voltage specifications are as follows. v ih =2.5v min v il =0.8v max viha when rising when falling 1.5v typ vila 1.8v typ input voltage input pin 5v v ss 10k 100k 5v overcurrent thermal shutdown 50k 50k output pin pin 8 50k opened motor pin vref/4.9 v s s amplifier ? + input pin pin 19 output pin pin 16 5v v ss overcurrent opened motor pin thermal shutdown
STK672-640C-E no. a2116-14/27 fault1 output fault1 is an open drain output. low is output if either overcurrent or overheating is detected. fault2 output output is resistance divided (3 levels) and the type of abnormality detected is converted to the corresponding output voltage. ? opened motor pin: 10mv (typ) ? overcurrent: 2.5v (typ) ? overheat: 3.3v (typ) abnormality detection can be released by a resetb operation or turning v dd voltage on/off. to set the motor current detection circuit operates when pin is open, to monitor the reference voltage vrefop terminal. it is also possible to set any detectable current by connecting an external pull-up resistor to 5v supply. when 7 pins open, vrefop (typ) is 98 mv. in this case, detection current i oh d is expressed as follows. vefop = i oh d rs (rs: current detection resistor) detection current is 1.1a. now, detection current gr eater than 0.25a is i oh dx. reference voltage vrefopx is calculated as above. pull-up resistor rdx by pin 7 is calculated as follows. rdx = (180 rtx) (180 - rtx) rtx = (5.0v - vrefopx) ((1.0588 vrefopx) - 0.0765) (rdx and rtx unit is k ? ) *to disable pin open detection, please connect a 5v pull-up resistor of 10k to 15k ? . output pin pin 7 5v v ss 1.3v to opened motor pin detection circuit 17k 1k 180k - +
STK672-640C-E no. a2116-15/27 2. STK672-640C-E over current detection, overheat detection, and motor terminal open detection functions each detection function operates using a latch system and turns output off. because a reset signal is required to restore output operations, once the power supply, v dd , is turned off, you must either again apply power on reset with v dd on or apply a resetb=high low high signal. [motor terminal open detection] this hybrid ic is equipped with a function for detecting open output terminals to prevent thermal destruction of the mosfet due to repeated avalanche operation that occurs when an output terminal connected to the motor is open. the open condition is determined by checking the presence or absence of the flyback curr ent that flows in the motor inductance during the off period of the pwm cycle. detection is performed by using the fact that the flyback current does not flow when a motor terminal is open. when the current level drops, the difference with the gnd potential decreases, making detection difficult. the motor current that can be detected by motor terminal open detection is 1.1a or more with the STK672-640C-E. when enable changes from low to high and the stk672-6xxb-e performs constant-current pwm operation that flows a negative current during the 30 s period after the high edge, open detection may activate and stop the driver. the motor current setting voltage vref must be set so th at pwm operation is not performed within a period of 30 s after the high edge. if the motor current setup voltage is set for the rated moto r current, pwm operation is not performed during this 30 s period after the high edge, so this is not a problem. in addition, there is no problem with operation that lowers the current setting vref after the motor rated current is reached as shown in the diagram on the following page. whether constant-current pwm operation is performed during the 30 s period after the high edge can be judged by substituting the motor l and r values into the formula on the following page. vref= (r02 (r01+r02)) 5v (or 3.3v) i oh 1= (vref 4.9) rs i oh 1: motor current value to be set i oh 2= (v cc r) (1-e -tr/l ) i oh 2: current value 30 s after the enable high edge ? judgment standard: i oh 1 > i oh 2 r01, r02, 5v (or 3.3v): see the sample application circuit documents. rs: current detection resistance value ( ) v cc : motor supply voltage (v) r: motor winding resistance ( ) l: motor winding inductance (h) ? there is no problem if the i oh 2 obtained by substituting t = 30 s and the motor l and r values is smaller than the current setting value i oh 1. used to see the motor current used for open detection (negative current does not flow when the terminal is open.) current detection resistor voltage 0v (gnd potential) mosfet gate signal terminal open pwm period
STK672-640C-E no. a2116-16/27 capacitors must not be connected between the phase a (pin 4), phase ab (pin 5), phase b (pin 3) and phase bb (pin 1) outputs and gnd. what happens if capacitors are connected is that open-circuit detection may be triggered by the discharge current of the capacitors when the intern al mosfet is set on. this current is not an inductance current generated by the motor winding but a capacitor current so a negative current will not flow to the other phase in each pair of phases, possibly cau sing the driver to shut down. if, when the motor current rises prior to the pwm opera tion, a spike-shaped current exceeding the vref-setting current is generated by excessive exte rnal noise, for instance, before the current level (0.7a for the stk672-632c-e and 630c-e, 1.1a for the stk672-642c-e and 640c-e moto r drivers) at which motor pin open-circuiting can be detected is reached, the internal mosfet is set off. since the mosfet has been set off before the actual moto r current reaches 0.5a (or 0.8a), the level of the negative current subsequently flowing to the other phase in each pair of phases is low, and it may be judged that no negative current is flowing, possibly causing open-circuit detection to be triggered. during normal constant-current pwm operation, the duration of 5.5 s, which is equivalent to 25% of the initial operation in the pwm period, corresponds to the section wher e the current is not detected, and this ensu res that no current is detected for the linking part of the current that is generated in this section. the no-current detection section is not synchronized at the current rise prior to the pwm operation so when a sp ike-shaped current exceeding the vref-setting current is generated, the mosfet is set off at the stage where the le vel of the actual motor current is low. as a result, the level of the negative current subsequently flowing to the other phase in each pair of phases is low, and it may be judged that no negative current is flowing, possibl y causing open-circuit detection to be triggered. motor current pwm period no-current detection time (5.5
STK672-640C-E no. a2116-17/27 [over current detection] this hybrid ic is equipped with a function for detecting over current that arises when the motor burns out or when there is a short between the motor terminals. over current detection occurs at 5.5a typ with the STK672-640C-E. over current detection begins after an interval of no detection (a dead time of 5.5 s typ) during the initial ringing part during pwm operations. the no detection interval is a peri od of time where over current is not detected even if the current exceeds i oh . [overheat detection] rather than directly detecting the temperature of the semi conductor device, overheat dete ction detects the temperature of the aluminum substrate (144 c typ). within the allowed operating range reco mmended in the specification manual, if a heat sink attached for the purpose of reducing the operating substrate temp erature, tc, comes loose, the semic onductor can operate without breaking. however, we cannot guarantee operations without breaking in the case of operations other than those recommended, such as operations at a current exceeding i oh max that occurs before over current detection is activated. 5.5 s typ) mosfet all off over current detection operation when motor pins are shorted current when motor terminals are shorted
STK672-640C-E no. a2116-18/27 3. calculating STK672-640C-E hic internal power loss the average internal power loss in each excitation mode of the STK672-640C-E can be ca lculated from the following formulas. each excitation mode 2-phase excitation mode 2pdavex=2 vsat 0.5 clock i oh t2+0.5 clock i oh (vsat t1+vdf t3) 1-2 phase excitation mode 1-2pdavex=2 vsat 0.25 clock i oh t2+0.25 clock i oh (vsat t1+vdf t3) motor hold mode holdpdavex= (vsat+vdf) i oh vsat: combined voltage of ron voltage drop + current detection resistance vdf: combined voltage of the fet body diode + current detection resistance clock: input clock (clock pin signal frequency) t1, t2, and t3 represent the waveforms shown in the figure below. t1: time required for the winding cu rrent to reach the set current (i oh ) t2: time in the constant current control (pwm) region t3: time from end of phase input signal until inverse current regeneration is complete motor com current waveform model t1= (-l/(r+0.20)) ln (1-((r+0.20)/v cc ) i oh ) t3= (-l/r) ln ((v cc +0.20)/(i oh r+v cc +0.20)) v cc : motor supply voltage (v) l: motor inductance (h) r: motor winding resistance ( ) i oh : motor set output current crest value (a) relationship of clock, t1, t2, and t3 in each excitation mode 2-phase excitation mode: t2= (2/clock) - (t1+t3) 1-2 phase excitation mode: t2= (3/clock) -t1 for vsat and vdf, be sure to substitute values from the graphs of vsat vs. i oh and vdf vs. i oh while the set current value is i oh . then, determine whether a heat sink is re quired by comparing with the graph of tc vs. pd based on the average hic power loss calculated. when designing a heat sink, refer to the section ?thermal design? found on the next page. the average hic power loss, pdav, described above does not have the avalanche?s loss. to include the avalanche?s loss, be sure to add equation (2), ?stk672-6** allowable avalanche energy valu e? to pdav above. when using this ic without a fin always check for temperature increases in the set, because the hic substrate temp erature, tc, varies due to effects of convection around the hic. i oh 0a t1 t2 t3
STK672-640C-E no. a2116-19/27 STK672-640C-E output saturation voltage, vsat - output current, i oh STK672-640C-E forward voltage, vdf -output current, i oh substrate temperature rise, tc (no heat sink) - internal average power dissipation, pdav 80 20 10 0 0 1.0 2.0 3.0 3.5 0.5 1.5 2.5 tc - pdav hybrid ic internal average power dissipation, pdav - w substrate temperature rise, tc - c itf02551 50 70 60 40 30 0 0.5 1.0 1.5 2.5 4.5 3.5 3.0 2.0 4.0 0.4 0.2 0 itf02589 1.0 0.8 0.6 2 5 c t c = 1 05 c vsat - i oh output current, i oh - a output saturation voltage, vsat - v 0 0.5 1.0 1.5 4.5 3.5 2.5 3.0 2.0 4.0 0.4 0.2 0 itf02590 1.4 1.0 1.2 0.8 0.6 t c = 2 5 c 1 0 5 c vdf- i oh output current, i oh - a forward voltage, vdf - v
STK672-640C-E no. a2116-20/27 4. STK672-640C-E allowabl e avalanche energy value (1) allowable range in avalanche mode when driving a 2-phase stepping motor with constant current chopping using an stk672-6** series hybrid ic, the waveforms shown in figure 1 belo w result for the output current, i d , and voltage, v ds . figure 1 output current, i d , and voltage, v ds , waveforms 1 of the stk672-6** series when driving a 2-phase stepping motor with constant current chopping when operations of the mosfet built into stk672-6** seri es ics is turned off for constant current chopping, the i d signal falls like the waveform shown in the figure above. at this time, the output voltage, v ds , suddenly rises due to electromagnetic induction generated by the motor coil. in the case of voltage that rises suddenly , voltage is restricted by the mosfet v dss . voltage restriction by v dss results in a mosfet avalanche. during avalanche operations, i d flows and the instantaneous energy at this time, eavl1, is represented by equation (1). eavl1=v dss iavl 0.5 tavl ------------------------------------------- (1) v dss : v units, iavl: a units, tavl: sec units the coefficient 0.5 in equation (1) is a constant required to convert the iavl triangle wave to a square wave. during stk672-6** series operations, the waveforms in the figure above repeat due to the constant current chopping operation. the allowable avalanche energy, eavl, is therefore represented by equation (2) used to find the average power loss, pavl, during avalanche mode multiplied by the chopping frequency in equation (1). pavl=v dss iavl 0.5 tavl fc ------------------------------------------- (2) fc: hz units (fc is set to the pwm frequency of 50khz.) for v dss , iavl, and tavl, be sure to actually operate th e stk672-6** series and substitute values when operations are observed using an oscilloscope. ex. if v dss =110v, iavl=1a, tavl=0.2 s when using a STK672-640C-E driver, the result is: pavl=110 0.5 0.5 0.2 10 -6 50 10 3 =0.28w v dss =110v is a value actually measured using an oscilloscope. the allowable loss range for the allowable avalanche ener gy value, pavl, is shown in the graph in figure 3. when examining the avalanche energy, be sure to actually drive a motor and observe the i d , v dss , and tavl waveforms during operation, and then check that the result of calculating equation (2) falls within the allowable range for avalanche operations. v dss : voltage during avalanche operations i oh : motor current peak value iavl: current during avalanche operations tavl: time of avalanche operations v ds i d itf02557
STK672-640C-E no. a2116-21/27 (2) i d and v dss operating waveforms in non-avalanche mode although the waveforms during avalanche mode are given in figure 1, sometimes an avalanche does not result during actual operations. factors causing avalanche are listed below. ? poor coupling of the motor?s phase coils (electromagnetic coupling of a phase and ab phase, b phase and bb phase). ? increase in the lead inductance of the harness caused by the circuit pattern of the p.c. board and motor. ? increases in v dss , tavl, and iavl in figure 1 due to an increase in the supply voltage from 24v to 36v. if the factors above are negligible, the waveforms shown in figure 1 become waveforms without avalanche as shown in figure 2. under operations shown in figure 2, avalanche does not occur and there is no need to consider the allowable loss range of pavl shown in figure 3. figure 2 output current, i d , and voltage, v ds , waveforms 2 of the stk672-6** series when driving a 2-phase stepping motor with constant current chopping figure 3 allowable loss range, pavl-i oh during STK672-640C-E avalanche operations note: the operating conditions given above represent a loss when driving a 2-phase stepping motor with constant current chopping. because it is possible to apply 3w or more at i oh =0a, be sure to avoid using the mosfet body diode that is used to drive the motor as a zener diode. i oh : motor current peak value v ds i d itf02558 0 0.5 1.0 1.5 2.5 2.0 3.5 3.0 1.0 0.5 0 itf02591 5.0 3.5 4.5 2.5 3.0 4.0 2.0 1.5 t c = 8 0 c 1 0 5 c pavl - i oh motor phase current, i oh - a average power loss in the avalanche state, pavl- w
STK672-640C-E no. a2116-22/27 5. thermal design [operating range in which a heat sink is not used] use of a heat sink to lower the operating substrate temperat ure of the hic (hybrid ic) is effective in increasing the quality of the hic. the size of heat sink for the hic varies depending on the magnitude of the average power loss, pdav, within the hic. the value of pdav increases as the output current increases. to calculate pdav, refer to ?calculating internal hic loss for the STK672-640C-E in the specification document. calculate the internal hic loss, pdav, assuming repeat operation such as shown in figure 1 below, since conduction during motor rotation and off time both exist during actual motor operations, figure 1 motor current timing t1: motor rotation operation time t2: motor hold operation time t3: motor current off time t2 may be reduced, depending on the application. t0: single repeated motor operating cycle i o 1 and i o 2: motor current peak values due to the structure of motor windings, the phase current is a positive and negative current with a pulse form. note that figure 1 presents the concepts here, and that the on/off duty of the actual signals will differ. the hybrid ic internal average power dissipation pdav can be cal culated from the following formula. pdav= (t1 p1+t2 p2+t3 0) to ---------------------------- (i) (here, p1 is the pdav for i o 1 and p2 is the pdav for i o 2) if the value calculated using equation (i) is 1.5w or less, and the ambient temperature, ta, is 60 c or less, there is no need to attach a heat sink. refer to figure 2 for operating substrate temperature data when no heat sink is used. [operating range in which a heat sink is used] although a heat sink is attached to lower tc if pdav in creases, the resulting size can be found using the value of c-a in equation (ii) below and the graph depicted in figure 3. c-a= (tc max-ta) pdav ---------------------------- (ii) tc max: maximum operating substrate temperature =105 c ta: hic ambient temperature although a heat sink can be designed based on equations (i) and (ii) above, be sure to mount the hic in a set and confirm that the substrate temperature, tc, is 105 c or less. the average hic power loss, pdav, described above represents the power loss when there is no avalanche operation. to add the loss during avalanche operations, be sure to add equation (2), ?allowable stk672-6** avalanche energy value?, to pdav. i o 1 i o 2 -i o 1 0a t1 t2 t3 t0 motor phase current (sink side)
STK672-640C-E no. a2116-23/27 figure 2 substrat e temperature rise, tc (no heat sink) - internal average power dissipation, pdav figure 3 heat sink area (board thickness: 2mm) - c-a 6. mitigated curve of package power loss, pdpk, vs. ambient temperature, ta package power loss, pdpk, refers to the average internal power loss, pdav, allowable without a heat sink. the figure below represents the allowable power loss, pd pk, vs. fluctuations in the ambient temperature, ta. power loss of up to 3.1w is allowable at ta=25 c, and of up to 1.75w at ta=60 c. allowable power dissipation, pdpk(no heat sink) - ambient temperature, ta 2 1.0 2 100 7 10 35 2 7 35 1000 c-a - s heat sink area, s - cm 2 heat sink thermal resistance, c-a - c/w itf02554 5 100 3 10 7 2 5 3 7 w i t h n o s u r f a c e f i n i s h w i t h a f l a t b l a c k s u r f a c e f i n i s h 1.0 0.5 0 080 20 40 60 100 120 pdpk - ta ambient temperature,ta - c allowable power dissipation, pdpk - w itf02511 2.5 3.0 3.5 2.0 1.5 80 20 10 0 0 1.0 2.0 3.0 3.5 0.5 1.5 2.5 tc - pdav hybrid ic internal average power dissipation, pdav - w substrate temperature rise, tc - c itf02553 50 70 60 40 30
STK672-640C-E no. a2116-24/27 7. example of stepping motor driver out put current path (1-2 phase excitation) clock i o a i o ab phase a output current phase ab output current pwm operations when pwm operations of i o a are off, for i o ab, negative current flows through the parasitic diode, f2. when pwm operations of i o ab are off, for i o a, negative current flows through the parasitic diode, f1. 2-phase stepping motor p.gnd c02 at least 100 f v cc 24v i o a i o ab phase excitation signal generation excitatin mode setting phase advnce counter a i bi v ss powe r on reset chopper circuit ove r current detection opened motor pin detection fault1, fault2 signal over heat detection v dd vref f1 f2 f3 f4 p.g2 r1 r2 vrefop a p.g1 v ss vref/4.9 a mp a b bbb fault2 latch latch latch 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 v dd =5v fault1 enable resetb cwb clock mode2 n.c mode1 n.c vre f fao fab fbo fbb
STK672-640C-E no. a2116-25/27 8. other notes on use in addition to the ?notes? indicated in the sample application circuit, care should also be given to the following contents during use. (1) allowable operating range operation of this product assumes use within the allo wable operating range. if a supply voltage or an input voltage outside the allowable operating range is applied, an overvoltage may damage the internal control ic or the mosfet. if a voltage application mode that exc eeds the allowable operating range is anticipated, connect a fuse or take other measures to cut off power supply to the product. (2) input pins if the input pins are connected directly to the pc board connectors, electrostatic discharge or other overvoltage outside the specified range may be applied from the connectors and may damage the product. current generated by this overvoltage can be suppressed to effectively prevent damage by inserting ? 100 to 1k resistors in lines connected to the input pins. take measures such as inserting resistors in lines connected to the input pins. (3) power connectors if the motor power supply v cc is applied by mistake without connectin g the gnd part of the power connector when the product is operated, such as for test purposes, an overcurrent flows through the v cc decoupling capacitor, c1, to the parasitic diode between the v dd of the internal control ic and gnd, and may damage the power supply pin block of the internal control ic. to prevent destruction in this case, connect a 10 resistor to the v dd pin, or insert a diode between the v cc decoupling capacitor c1 gnd and the v dd pin. (4) input signal lines 1) do not use an ic socket to mount the driver, and instead solder the driver directly to the pc board to minimize fluctuations in the gnd potential due to the influence of the resistance component and inductance component of the gnd pattern wiring. 2) to reduce noise caused by electro magnetic induction to small signal lines, do not design small signal lines (sensor signal lines, and 5v or 3.3v power supply signal lines) that run parallel in close proximity to the motor output line a (pin 4), ab (pin 5), b (pin 3), or bb (pin 1) phases. 3) pin 11 of this product are n.c pins. do not connect any wiring to these pins. overcurrent protection measure: insert a resistor. overcurrent protection measure: insert a diode. over-current path 5v reg. 24v reg. mode1 fao c1 r1 r2 gnd open fabo fbo fbbo ai bi vref v dd v dd =5v v cc v ss clock cwb resetb enable mode2 fault1 vref n.c 9 18 4 2 6 a 5 ab 3 b 1 bb f1 f2 f3 f4
STK672-640C-E no. a2116-26/27 (5) when mounting multiple drivers on a single pc board when mounting multiple drivers on a single pc board, the gnd design should mount a v cc decoupling capacitor, c1, for each driver to stabili ze the gnd potential of the other drivers. the key wiring points are as follows. (6) v cc operating limit when the output (for example f1) of a 2-phase stepping motor driver is turned off, the ab phase back electromotive force eab produced by current flowing to the paired f2 parasitic diode is induced in the f1 side, causing the output voltage vfb to become twice or more the v cc voltage. this is expressed by the following formula. vfb = v cc + eab = v cc + v cc + i oh rm + vdf (1.5 v) v cc : motor supply voltage, i oh : motor current set by vref vdf: voltage drop due to f2 parasitic diode and curre nt detection resistor r1, rm: motor winding resistance value using the above formula, make sure that vfb is always less than the mosfet withst and voltage of 100v. this is because there is a possibility that operating limit of v cc falls below the allowable operating range of 46v, due to the rm and i oh specifications. the oscillating voltage in excess of vfb is caused by l crm (inductance, capacitor, re sistor, mutual inductance) oscillation that includes micro capacitors c, not presen t in the circuit. since m is affected by the motor characteristics, there is some differen ce in oscillating voltage according to the motor specifications. in addition, constant voltage drive without constant current drive enables motor rotation at v cc 0v. f1 on f2 off v cc r1 m f1 off f2 off v cc r1 m gnd gnd a p hase ab phase ab p hase a p hase vfb v cc eab the pass of drain current the pass of negative current eab eab is induced by inducing m. 2 5v 9 19 18 6 ic1 moto r 1 short thick thick and short gnd 24v gnd 9 19 18 2 6 ic2 moto r 2 9 19 18 2 6 ic3 moto r 3 input signals input signals input signals
STK672-640C-E no. a2116-27/27 ps sanyo semiconductor co.,ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. regarding monolithic semiconductors, if you should intend to use this ic continuously under high temperature, high current, high voltage, or drastic temperature change, even if it is used within the range of absolute maximum ratings or operating conditions, there is a possibility of decrease reliability. please contact us for a confirmation. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equ ipment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. this catalog provides information as of august, 2012. specifications and information herein are subject to change without notice.

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